Hello,
in Simatic Step7 V5.6 I used FC92 function block for shift bits in register.
After that I migrated that aplication in TIA Step7 (for new CPU 1500), and I got error during migration.
After that I read that CPU1500 not support MCR, MCRA, MCRD instruction ant that is reason why the problem exist.
Can someone help me and is there any another function which I can use for shift bits in register for CPU 1500?
Best regards.
FC92 SHRB SHIFT Shift bit in the shift register
from "TI-S7 Converting Blocks" library
FUNCTION "SHRB" : VOID
TITLE = BIT SHIFT REGISTER
AUTHOR : SEA
FAMILY : SHIFT
NAME : SHRB
VERSION : 2.0
VAR_INPUT
DATA : BOOL ; // source data bit
RESET : BOOL ; // resets the shift register
S_BIT : POINTER ; // points to the start bit in the shift register
N : WORD ; // length of shift register (number of bits to be shifted)
END_VAR
VAR_TEMP
BLKNO : WORD ;
SAVBIT : BOOL ;
SAVNXT : BOOL ;
TMP : BOOL ;
END_VAR
BEGIN
NETWORK
TITLE =
L #N;
L 1;
<I ;
JC DONE;
SET ;
AN #RESET;
MCR( ;
// Open DB and set ptr
L P##S_BIT;
LAR1 ; // Addr.Reg1 = Ptr to Src. Table
L W [AR1,P#0.0]; // load Block No. into accum 1
T #BLKNO; // scrblk = Block No.
OPN DB [#BLKNO]; // opens 1st Block, DB
L D [AR1,P#2.0]; // load Block Area Reference
LAR1 ; // load Block Addr.(area ref.)into Addr.Reg1
SET ; // place DATA into SAVNXT & SAVBIT
A #DATA;
= #SAVNXT;
= #SAVBIT;
L #N;
SHFT: T #N;
MCRA ;
SET ;
A [AR1,P#0.1];
= #SAVNXT; // SAVNXT = P#0.1
//-------------------
SET ;
A [AR1,P#0.0];
= #TMP; // TMP = P#0.0
//-------------------
SET ;
A #SAVBIT;
= [AR1,P#0.0]; // P#0.0 = SAVBIT
//-------------------
SET ;
A #TMP;
= #SAVBIT; // SAVBIT = TMP
//-------------------
+AR1 P#0.1; // Increment pointer to next bit
MCRD ;
L #N;
LOOP SHFT;
)MCR ;
DONE: SET ;
SAVE ;
END_FUNCTION
daca2309 wrote: Sat Feb 27, 2021 9:08 am
And this code is not useful.
May be SCL code will be more useful for TIA.
The POINTER I changed to 3 INT variables (see picture).
I small checked it with original FC92 they are working identically.
FUNCTION FC192 : VOID
TITLE = 'BIT SHIFT REGISTER'
AUTHOR : SEA
FAMILY : SHIFT
NAME : SHRB
VERSION : '2.0'
//KNOW_HOW_PROTECT
VAR_INPUT
DATA : BOOL; // source data bit
RESET : BOOL; // resets the shift register
DBNo : INT; // DB number
sIDX : INT; // start index in the shift register
sBIT : INT; // start bit in the shift register
N : WORD ; // length of shift register (number of bits to be shifted)
END_VAR
VAR_TEMP
BLKNO : WORD;
SAVBIT : BOOL;
SAVNXT : BOOL;
TMP : BOOL;
STR : DINT;
END : DINT;
i : DINT;
ni : DINT;
nb : DINT;
nip : DINT;
nbp : DINT;
END_VAR
BEGIN
IF WORD_TO_DINT(N) >= 1 THEN
STR := sIDX * 8 + sBIT;
END := STR + WORD_TO_DINT(N) - 1;
BLKNO := INT_TO_WORD(DBNo);
SAVNXT := DATA;
SAVBIT := DATA;
IF NOT RESET THEN
FOR i := STR TO END BY 1 DO
ni := i DIV 8;
nb := i MOD 8;
nip := (i+1) DIV 8;
nbp := (i+1) MOD 8;
SAVNXT := WORD_TO_BLOCK_DB(BLKNO).DX[nip,nbp];
TMP := WORD_TO_BLOCK_DB(BLKNO).DX[ni,nb];
WORD_TO_BLOCK_DB(BLKNO).DX[ni,nb] := SAVBIT;
SAVBIT := TMP;
END_FOR;
ELSE
FOR i := STR TO END BY 1 DO
ni := i DIV 8;
nb := i MOD 8;
SAVNXT := FALSE;
TMP := FALSE;
WORD_TO_BLOCK_DB(BLKNO).DX[ni,nb] := FALSE;
SAVBIT := FALSE;
END_FOR;
END_IF;
END_IF;
END_FUNCTION
I tried it. But there is problem using for S7 1500 plc.
WORD_TO_BLOCK_DB(#BLKNO).DX[#nip, #nbp] cannot be used. In Library list, doesnot exist. Maybe for S7300/S7 400 cpu it is possible.
I can't compile it.
BR.